1. Field of the Invention
This invention relates to an interface circuit in a semiconductor integrated circuit (IC), and more particularly to an interface circuit serving as an interface between a circuit of high power supply voltage system and a circuit of low power supply voltage system which commonly use a bus line.
2. Description of the Related Art
Conventionally, semiconductor elements formed based on the 0.8 micron design rule, for example, are operated on a power supply voltage of 5V. In contrast, it is intended that semiconductor elements formed by the fine pattern technology based on the 0.5 micron design rule, for example, are operated on a power supply voltage of 3.3V or 3.0V since the gate oxide film thereof is made thin and the withstanding voltage thereof is lowered (generally, it is estimated to be 3.6V).
In a case where an IC which is forced to be operated on a low power supply voltage because of a reduction in the withstanding voltage due to miniaturization of the elements is used together with an IC of 5V system, the IC of low power supply voltage system is sometimes used in an interface circuit with a signal system having a signal amplitude (for example, 5V) higher than the withstanding voltage thereof.
FIG. 1 schematically shows the construction of a circuit in which an IC of low power supply voltage (for example, 3.3V) system and an IC of high power supply voltage (for example, 5V) system commonly use a bus line. An IC 91 of 3.3V system and ICs 92-1, 92-2 of 5V system are connected together via a bus line 93. In the IC 91, an output circuit 91a operated on a power supply voltage of 3.3V is provided, and in the IC 92-1, an output circuit 92a operated on a power supply voltage of 5V is provided. The output circuits 91a, 92a are supplied with output enable signals OE, OE respectively and the output states thereof are controlled. Further, in the IC 92-2, an input circuit 92b operated on a power supply voltage of 5V is provided.
With the above construction, a voltage of 5V is applied from the output circuit 92a to the output node of the output circuit 91a used as an interface circuit in the IC 91 of 3.3V system via the bus line 93. Therefore, the output circuit 91a is required to have a withstanding voltage equal to or higher than 5V.
FIG. 2 shows an example of the construction of an output stage in the output circuit 91a of the IC 91 of 3.3V system in the circuit shown in FIG. 1. The circuit is constructed by a P-channel MOS transistor (which is hereinafter referred to as a PMOS transistor) P1, N-channel MOS transistor (which is hereinafter referred to as an NMOS transistor) N1, and depletion type NMOS transistor N2. The current paths of the PMOS transistor P1 and NMOS transistor N1 are serially connected between a power supply Vcc (=3.3V) and a ground terminal Vss. The gate potentials of the MOS transistors P1, N1 are selectively controlled by an output signal from the internal circuit, the output node Na is selectively set to one of the "H" level, "L" level and high impedance state, and thus they function as a tri-state buffer. The NMOS transistor N2 whose source-drain path is connected between the output node Na and an output terminal Nb of the IC 91 functions to separate the output node Na of the tri-state buffer from the IC 92-1 of 5V system, the gate thereof is connected to the power supply Vcc and the backgate thereof is fixed at the ground potential Vss.
The NMOS transistor N2 outputs a voltage near the power supply voltage Vcc to the output terminal Nb when the potential of the output node Na of the tri-state buffer is set at the "H" level. Therefore, if the threshold voltage of the NMOS transistor N2 is always kept at 0V, a voltage of 3.3V is output from the output node Nb of the IC 91. The NMOS transistor N2 must be so designed that, if 5V is applied to one end (output terminal Nb of the IC 91) of the current path of the NMOS transistor N2 via the bus line 93 when the output node Na of the tri-state buffer is set in the high impedance state, a voltage which is not higher than the withstanding voltage of an element of 3.3V system will not appear on the other end (output node Na of the tri-state buffer) of the current path. The reason is that, if a voltage which is higher than the withstanding voltage of the element of 3.3V system appears on the output node Na, an excessively high voltage is applied between the gate and drain of the NMOS transistor N1 since 3.3V is applied to the gate of the PMOS transistor P1 and 0V is applied to the gate of the NMOS transistor N1, and as a result, the reliability of the NMOS transistor N1 may be degraded and the gate insulation film may be destroyed. Therefore, it is necessary to suppress the potential of the node Na within a permitted voltage range.
Therefore, it becomes necessary to determine the threshold voltage of the depletion type NMOS transistor by taking the backgate Bias effect into consideration so as to satisfy the above two limitations, that is, the limitation that the power supply voltage Vcc is output from the output terminal Nb of the IC 91 when the potential of the node Na is at the "H" level and the limitation that the potential of the node Na is suppressed within the permitted voltage range if 5V is applied to the output terminal Nb of the IC 91 via the bus line when the node Na is set at the high impedance state.
Next, the threshold voltage Vthn2 of the NMOS transistor N2 is considered.
First, assume that the power supply voltage range of the 3.3V system is 3.3V.+-.0.3V, the maximum value of the gate withstanding voltage of the element is 3.6V, and the range of a signal of 5V system supplied to the bus line 93 is 5.0V.+-.0.5V. Further, assume that the input voltage range of a circuit portion which receives a signal appearing on the bus line 93 is defined by the TTL level (V.sub.H =2.0V, V.sub.L =0.8V). In this case, assume that V.sub.H =2.7V must be finally stably attained in a circuit portion for outputting a signal since a DC through current of a receiver side circuit becomes larger when V.sub.H =2.0V. This is not a particular limitation. This is because the output voltage V.sub.OH of TTL is normally 2.7V.
Therefore, a voltage of 2.7V or more must be stably attained as the output voltage of the IC 91 when the potential of the node Na is at the "H" level. In the output mode of "H" level, the limitation becomes severest when an output voltage of 2.7V or more is stably attained in the case of the minimum power supply voltage level (3V) of 3.3V system, and the threshold voltage Vthn2 must be set equal to or lower than 0.3V when taking the backgate bias effect into consideration and if the substrate bias potential V.sub.BS is -2.7V.
Assuming now that the threshold voltage Vthn2 is changed by 0.3V for a variation of -1V in the substrate bias potential V.sub.BS as the backgate bias effect and if the threshold voltage of the depletion NMOS transistor N2 at the time of V.sub.BS =0V (in a state in which no backgate bias effect is present) is expressed by Vth(V.sub.BS =0), the following equation is obtained. EQU Vth(V.sub.BS =0)+2.7V.times.0.3V=0.3V
That is, the relation of Vth(V.sub.BS =0)=-0.51V must be satisfied and a characteristic indicated by the solid line La can be obtained.
In contrast, when the potential of the node Na is at the "L" level, no problem concerning the threshold voltage Vthn2 occurs.
On the other hand, if 5V is applied to the output terminal Nb of the IC 91 via the bus line 93 when the node Na is set in the high impedance state, the potential of the node Na is pulled by the applied voltage and rises. At this time, if the withstanding voltage between the gate and drain of the NMOS transistor N1 is considered, the potential of the node Na must not be set equal to or higher than 3.6V. The potential Va of the node Na is controlled by the gate potential V.sub.G2 of the depletion type NMOS transistor N2. That is, it rises to a potential to satisfy the relation of V.sub.G2 -Va-Vthn2=0V. Therefore, Vthn2=0V must be satisfied when V.sub.G2 =3.6V and Va=3.6V. Further, it is necessary to satisfy the relation that Vth(V.sub.BS =0)+3.6V.times.0.3V=0V, that is, Vth(V.sub.BS =0)=-1.08V and a characteristic as indicated by the solid line Lb in FIG. 3 can be obtained.
As described above, the threshold voltage Vthn2 of the NMOS transistor N2 must lie in a region between the solid lines La and Lb shown in FIG. 3 and the margin of the threshold voltage Vthn2 is 0.57V.
Next, like the consideration for the 3.3V system, a case wherein the IC 91 having an output circuit shown in FIG. 2 is operated on a 3V system is considered. In this case, assume that the range of the power supply voltage of 3V system is 3.0V.+-.0.3V, the maximum value of the gate withstanding voltage of the element is 3.6V, and the range of a signal of 5V system applied to the bus line is 5.0V.+-.0.5V. In this case, a characteristic as indicated by a one-dot-dash line Lc in FIG. 3 can be obtained as the threshold voltage Vthn2 of the NMOS transistor N2 necessary for stably attaining an output voltage of 2.7V or more of the IC 91 when the potential of the node Na is at the "H" level. Further, characteristic as indicated by a two-dot-dash line Ld in FIG. 3 can be obtained as the threshold voltage Vthn2 necessary for suppressing the potential of the node Na to a value equal to or lower than 3.6V if 5V is applied to the output terminal Nb of the IC 91 via the bus line 93 when the node Na is set in the high impedance state.
When taking the above-described fact into consideration, the threshold voltage Vthn2 of the NMOS transistor N2 must be set within a range between the one-dot-dash line Lc and the two-dot-dash line Ld in FIG. 3 and the margin of the threshold voltage Vthn2 set at this time is 0.48V.
When considering the temperature dependency (-2 to -3 mV/.degree.C.) of the threshold voltage Vthn2, a variation of approx. .+-.0.2V will occur with respect to a value obtained at the temperature of 25.degree. C. in the temperature range of -40.degree. C. to 85.degree. C., for example, and therefore, it becomes necessary to precisely control the degree of process fluctuation of the threshold voltage Vthn2 in the 3.3V system and it is also necessary to further precisely control a variation in the threshold voltage Vthn2 in the 3V system.
Thus, the output circuit of the conventional IC shown in FIG. 2 has a disadvantage that the operation margin for a variation in the threshold voltage Vthn2 of the depletion type NMOS transistor N2 inserted for separation of the output node Na of the tri-state buffer from the bus line 93 is small and the process control is difficult.